PIC18F258 Datasheet, PDF (85/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
REGISTER 8-5:
PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (PIR2)
U-0
R/W-0
U-0
—
CMIF⁽¹⁾
—
bit 7
R/W-0
EEIF
R/W-0
BCLIF
R/W-0
LVDIF
R/W-0
TMR3IF
R/W-0
ECCP1IF⁽¹⁾
bit 0
bit 7
Unimplemented: Read as ’0’
bit 6
CMIF: Comparator Interrupt Flag bit ⁽¹⁾
1 = Comparator input has changed
0 = Comparator input has not changed
bit 5
Unimplemented: Read as’0’
bit 4
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = Write operation is complete (must be cleared in software)
0 = Write operation is not complete
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 2
LVDIF: Low Voltage Detect Interrupt Flag bit
1 = A low voltage condition occurred (must be cleared in software)
0 = The device voltage is above the Low Voltage Detect trip point
bit 1
TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0
ECCP1IF: ECCP1 Interrupt Flag bit ⁽¹⁾
Capture mode:
1 = A TMR1 (TMR3) register capture occurred
(must be cleared in software)
0 = No TMR1 (TMR3) register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred
(must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ’0’.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
 2002 Microchip Technology Inc
Preliminary
DS41159B-page 83