PIC18F258 Datasheet, PDF (62/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
REGISTER 5-1:
EECON1 REGISTER
R/W-x R/W-x
U-0
EEPGD CFGS
—
bit 7
R/W-0
FREE
R/W-x
WRERR
R/W-0
WREN
R/S-0
WR
R/S-0
RD
bit 0
bit 7
EEPGD: FLASH Program or Data EEPROM Memory Select bit
1 = Access program FLASH memory
0 = Access data EEPROM memory
bit 6
CFGS: FLASH Program/Data EE or Configuration Select bit
1 = Access configuration registers
0 = Access program FLASH or data EEPROM memory
bit 5
Unimplemented: Read as '0'
bit 4
FREE: FLASH Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(reset by hardware)
0 = Perform write only
bit 3
WRERR: Write Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR or any WDT Reset during self-timed programming in normal operation)
0 = The write operation completed
Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing
of the error condition.
bit 2
WREN: Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM or FLASH memory
bit 1
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0 = Write cycle is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS41159B-page 60
Preliminary
 2002 Microchip Technology Inc.