PIC18F258 Datasheet, PDF (348/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
FIGURE 27-15:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
Bit6 - - - - - -1
LSb
75, 76
77
SDI
MSb In
Bit6 - - - -1
LSb In
74
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-16: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70 TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
71 TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72 TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73A TB2B
Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40 —
74 TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75 TdoR
SDO data output rise time
PIC18FXX8
—
25
PIC18LFXX8
—
45
76 TdoF
SDO data output fall time
—
25
77 TssH2doZ SS↑ to SDO output hi-impedance
78 TscR
SCK output rise time
(Master mode)
PIC18FXX8
PIC18LFXX8
79 TscF
SCK output fall time (Master mode)
80 TscH2doV, SDO data output valid after SCK PIC18FXX8
TscL2doV edge
PIC18LFXX8
10
50
—
25
—
45
—
25
—
50
—
100
82 TssL2doV SDO data output valid after SS↓ PIC18FXX8
edge
PIC18LFXX8
—
50
—
100
83 TscH2ssH, SS ↑ after SCK edge
TscL2ssH
Note 1: Requires the use of parameter # 73A.
2: Only if parameter #’s 71A and 72A are used.
1.5 TCY + 40 —
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS41159B-page 346
Preliminary
 2002 Microchip Technology Inc.