PIC18F258 Datasheet, PDF (73/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
6.5 Writing to FLASH Program
Memory
The minimum programming block is 4 words or 8 bytes.
Word or byte programming is not supported.
Table Writes are used internally to load the holding reg-
isters needed to program the FLASH memory. There
are 8 holding registers used by the Table Writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction has to be executed 8 times for
each programming operation. All of the Table Write
operations will essentially be short writes, because only
the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
The long write is necessary for programming the inter-
nal FLASH. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of
the device for byte or word operations.
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer with address being erased.
4. Do the row erase procedure.
5. Load Table Pointer with address of first byte
being written.
6. Write the first 8 bytes into the holding registers
using the TBLWT instruction, auto-increment
may be used.
7. Set the EECON1 register for the write operation:
• set the EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set the WREN to enable byte writes.
8. Disable interrupts.
9. Write 55h to EECON2.
10. Write AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Execute a NOP.
14. Re-enable interrupts.
15. Repeat steps 6-14 seven times, to write 64
bytes.
16. Verify the memory (Table Read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
Note 1: A NOP is needed after the WR command
to ensure proper code execution.
2: Before setting the WR bit, the Table
Pointer address needs to be within the
range of addresses of the 8 bytes in the
holding registers.
3: Holding registers are cleared on RESET
and at the completion of each write cycle.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
TBLPTR = xxxxx2
Holding Register
Holding Register
Holding Register
8
TBLPTR = xxxxx7
Holding Register
Program Memory
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 71