PIC18FXX8 Datasheet, PDF (91/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
REGISTER 8-11:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
U-0
R/W-1
U-0
—
CMIP⁽¹⁾
—
R/W-1
EEIP
R/W-1
BCLIP
R/W-1
LVDIP
bit 7
R/W-1
TMR3IP
R/W-1
ECCP1IP⁽¹⁾
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
CMIP: Comparator Interrupt Priority bit⁽¹⁾
1 = High priority
0 = Low priority
bit 5
Unimplemented: Read as ‘0’
bit 4
EEIP: EEPROM Write Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
LVDIP: Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
ECCP1IP: ECCP1 Interrupt Priority bit⁽¹⁾
1 = High priority
0 = Low priority
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
 2004 Microchip Technology Inc.
DS41159D-page 89