PIC18FXX8 Datasheet, PDF (291/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
AND W with f
[ label ] ANDWF f [,d [,a]]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) .AND. (f) → dest
N, Z
0001 01da ffff ffff
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden (default).
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
ANDWF
Before Instruction
W
=
REG =
After Instruction
W
=
REG =
0x17
0xC2
0x02
0xC2
REG, W
BC
Branch if Carry
Syntax:
[ label ] BC n
Operands:
-128 ≤ n ≤ 127
Operation:
if Carry bit is ‘1’
(PC) + 2 + 2n → PC
Status Affected: None
Encoding:
1110 0010 nnnn nnnn
Description:
If the Carry bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruc-
tion, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
Q2
Read literal
‘n’
No
operation
Q2
Read literal
‘n’
Q3
Process
Data
No
operation
Q3
Process
Data
Q4
Write to PC
No
operation
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Carry
=
PC
=
If Carry
=
PC
=
BC JUMP
address (HERE)
1;
address (JUMP)
0;
address (HERE + 2)
 2004 Microchip Technology Inc.
DS41159D-page 289