PIC18FXX8 Datasheet, PDF (303/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result = 0
Status Affected:
None
Encoding:
0010 11da ffff ffff
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as per
the BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ‘f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
Write to
destination
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
DECFSZ
GOTO
CONTINUE
CNT
LOOP
Before Instruction
PC
=
After Instruction
CNT =
If CNT =
PC =
If CNT ≠
PC =
Address (HERE)
CNT – 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
DCFSNZ
Decrement f, Skip if not 0
Syntax:
[ label ] DCFSNZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result ≠ 0
Status Affected:
None
Encoding:
0100 11da ffff ffff
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
Process
register ‘f’
Data
If skip:
Q1
Q2
Q3
No
No
No
operation operation operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
Write to
destination
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
ZERO
NZERO
DCFSNZ TEMP
:
:
Before Instruction
TEMP
After Instruction
TEMP
If TEMP
PC
If TEMP
PC
=?
= TEMP – 1,
= 0;
= Address (ZERO)
≠ 0;
= Address (NZERO)
 2004 Microchip Technology Inc.
DS41159D-page 301