PIC18FXX8 Datasheet, PDF (197/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
18.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous Master mode is selected, reception
is enabled by setting either enable bit SREN (RCSTA
register) or enable bit CREN (RCSTA register). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 18.1 “USART Baud Rate
Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend:
Note 1:
GIE/GIEH
PSPIF⁽¹⁾
PSPIE⁽¹⁾
PSPIP⁽¹⁾
PEIE/GIEL
ADIF
ADIE
ADIP
TMR0IE
RCIF
RCIE
RCIP
INT0IE
TXIF
TXIE
TXIP
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
TMR1IF
TMR1IE
TMR1IP
0000 000x
0000 0000
0000 0000
1111 1111
0000 000u
0000 0000
0000 0000
1111 1111
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000u
USART Receive Register
0000 0000 0000 0000
CSRC
TX9
TXEN SYNC
—
BRGH TRMT TX9D 0000 -010 0000 -010
Baud Rate Generator Register
0000 0000 0000 0000
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
FIGURE 18-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
 2004 Microchip Technology Inc.
DS41159D-page 195