PIC18FXX8 Datasheet, PDF (269/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
REGISTER 24-3:
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 7
bit 0
bit 7-4
bit 3-1
bit 0
Unimplemented: Read as ‘0’
WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
Note: The Watchdog Timer postscale select bits configuration used in the PIC18FXXX
devices has changed from the configuration used in the PIC18CXXX devices.
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
REGISTER 24-4:
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
U-0
U-0
U-0
U-0
R/P-1
U-0
R/P-1
DEBUG
—
—
—
—
LVP
—
STVREN
bit 7
bit 0
bit 7
bit 6-3
bit 2
bit 1
bit 0
DEBUG: Background Debugger Enable bit
1 = Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins.
0 = Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.
Unimplemented: Read as ‘0’
LVP: Low-Voltage ICSP Enable bit
1 = Low-Voltage ICSP enabled
0 = Low-Voltage ICSP disabled
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack Full/Underflow will cause Reset
0 = Stack Full/Underflow will not cause Reset
Legend:
R = Readable bit
C = Clearable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
 2004 Microchip Technology Inc.
DS41159D-page 267