PIC18FXX8 Datasheet, PDF (307/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
LFSR
Load FSR
Syntax:
[ label ] LFSR f,k
Operands:
0≤f≤2
0 ≤ k ≤ 4095
Operation:
k → FSRf
Status Affected: None
Encoding:
Description:
1110
1111
1110 00ff k₁₁kkk
0000 k₇kkk kkkk
The 12-bit literal ‘k’ is loaded into the
file select register pointed to by ‘f’.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Decode
Q2
Read literal
‘k’ MSB
Decode Read literal
‘k’ LSB
Q3
Process
Data
Process
Data
Q4
Write
literal ‘k’
MSB to
FSRfH
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 0x3AB
After Instruction
FSR2H
FSR2L
= 0x03
= 0xAB
MOVF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Move f
[ label ] MOVF f [,d [,a]]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
f → dest
N, Z
0101 00da ffff ffff
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding the
BSR value. If ‘a’ = 1, then the bank will
be selected as per the BSR value
(default).
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write W
Example:
MOVF
Before Instruction
REG
=
W
=
After Instruction
REG
=
W
=
REG, W
0x22
0xFF
0x22
0x22
 2004 Microchip Technology Inc.
DS41159D-page 305