PIC18FXX8 Datasheet, PDF (122/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
14.1 Timer3 Operation
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON register).
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is set),
the RC1/T1OSI and RC0/T1OSO/T1CKI pins become
inputs. That is, the TRISC<1:0> value is ignored.
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (Section 15.1
“CCP1 Module”).
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
TMR3IF
Overflow
Interrupt
Flag bit
T1OSO/
T1CKI
T1OSI
TMR3H
T1OSC
CLR
TMR3L
CCP Special Trigger
T3CCPx
0
Synchronized
Clock Input
TMR3ON
On/Off
1
T3SYNC
1
T1OSCEN _FOSC/4
Enable
Oscillator⁽¹⁾
Internal
Clock
0
TMR3CS
Prescaler
1, 2, 4, 8
2
Synchronize
det
Sleep Input
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
TMR3IF Overflow
Interrupt Flag
bit
8
TMR3
TMR3H
CLR
TMR3L
T1OSO/
T1CKI
T1OSI
To Timer1 Clock Input
T1OSC
T1OSCEN
Enable
Oscillator⁽¹⁾
CCP Special Trigger
T3CCPx
0
Synchronized
Clock Input
TMR3ON
On/Off
1
T3SYNC
1
FOSC/4
Internal 0
Clock
Prescaler
1, 2, 4, 8
2
T3CKPS1:T3CKPS0
TMR3CS
Synchronize
det
Sleep Input
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS41159D-page 120
 2004 Microchip Technology Inc.