PIC18FXX8 Datasheet, PDF (116/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON register).
When TMR1CS is clear, Timer1 increments every
instruction cycle. When TMR1CS is set, Timer1
increments on every rising edge of the external clock
input or the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (Section 15.1
“CCP1 Module”).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
TMR1IF
Overflow
Interrupt
Flag bit
T1CKI/T1OSO
T1OSI
CCP Special Event Trigger
TMR1
CLR
TMR1H TMR1L
T1OSC
T1OSCEN
Enable
Oscillator⁽¹⁾
Synchronized
0
Clock Input
TMR1ON
On/Off
1
T1SYNC
FOSC/4
Internal
Clock
1
Prescaler
1, 2, 4, 8
0
2
T1CKPS1:T1CKPS0
TMR1CS
Synchronize
det
Sleep Input
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
TMR1IF
Overflow
Interrupt
Flag bit
8
TMR1
Timer 1
High Byte
TMR1L
T1CKI/T1OSO
T1OSI
T1OSC
T1OSCEN
Enable
Oscillator⁽¹⁾
Special Event Trigger
0
Synchronized
Clock Input
TMR1ON
On/Off
1
T1SYNC
1
FOSC/4
Internal
Clock
0
TMR1CS
Prescaler
1, 2, 4, 8
2
Synchronize
det
Sleep Input
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
DS41159D-page 114
 2004 Microchip Technology Inc.