PIC18FXX8 Datasheet, PDF (278/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
24.4 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro devices.
The user program memory is divided into five blocks.
One of these is a boot block of 512 bytes. The remain-
der of the memory is divided into four blocks on binary
boundaries.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-3 shows the program memory organization
for 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
FIGURE 24-3:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18FXX8
MEMORY SIZE/DEVICE
16 Kbytes
(PIC18FX48)
32 Kbytes
(PIC18FX58)
Address
Range
Block Code Protection
Controlled By:
Boot Block
Block 0
Boot Block
Block 0
000000h
0001FFh
000200h
001FFFh
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
Block 1
Unimplemented
Read ‘0’s
Block 1
Block 2
002000h
003FFFh
004000h
005FFFh
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
Unimplemented
Read ‘0’s
Block 3
006000h
007FFFh
008000h
CP3, WRT3, EBTR3
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
300008h CONFIG5L
—
—
—
—
CP3
300009h CONFIG5H CPD
CPB
—
—
—
30000Ah CONFIG6L
—
—
—
—
WRT3
30000Bh CONFIG6H WRTD WRTB WRTC
—
—
30000Ch CONFIG7L
—
—
—
—
EBTR3
30000Dh CONFIG7H —
EBTRB
—
—
—
Legend: Shaded cells are unimplemented.
Bit 2
CP2
—
WRT2
—
EBTR2
—
Bit 1
CP1
—
WRT1
—
EBTR1
—
Bit 0
CP0
—
WRT0
—
EBTR0
—
DS41159D-page 276
 2004 Microchip Technology Inc.