PIC18FXX8 Datasheet, PDF (212/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
19.2.3 CAN RECEIVE BUFFER
REGISTERS
This section shows the Receive Buffer registers with
their associated control registers.
REGISTER 19-12: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER
R/C-0 R/W-0 R/W-0
RXFUL⁽¹⁾ RXM1⁽¹⁾ RXM0⁽¹⁾
U-0
R-0
R/W-0
— RXRTRRO RXB0DBEN
bit 7
R-0
JTOFF
R-0
FILHIT0
bit 0
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
RXFUL: Receive Full Status bit⁽¹⁾
1 = Receive buffer contains a received message
0 = Receive buffer is open to receive a new message
Note: This bit is set by the CAN module and must be cleared by software after the buffer
is read.
RXM1:RXM0: Receive Buffer Mode bits⁽¹⁾
11 = Receive all messages (including those with errors)
10 = Receive only valid messages with extended identifier
01 = Receive only valid messages with standard identifier
00 = Receive all valid messages
Unimplemented: Read as ‘0’
RXRTRRO: Receive Remote Transfer Request Read-Only bit
1 = Remote transfer request
0 = No remote transfer request
RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit
1 = Receive Buffer 0 overflow will write to Receive Buffer 1
0 = No Receive Buffer 0 overflow to Receive Buffer 1
JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN)
1 = Allows jump table offset between 6 and 7
0 = Allows jump table offset between 1 and 0
Note: This bit allows same filter jump table for both RXB0CON and RXB1CON.
FILHIT0: Filter Hit bit
This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0.
1 = Acceptance Filter 1 (RXF1)
0 = Acceptance Filter 0 (RXF0)
Note 1: Bits RXFUL, RXM1 and RXM0 of RXB0CON are not mirrored in RXB1CON.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit C = Clearable bit
‘1’ = Bit is set ‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
DS41159D-page 210
 2004 Microchip Technology Inc.