PIC18FXX8 Datasheet, PDF (249/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

20.4 A/D Conversions
Figure 20-4 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D Result register pair will not be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL
registers). After the A/D conversion is aborted, a 2 TAD
wait is required before the next acquisition is started.
After this 2 TAD wait, acquisition on the selected
channel is automatically started.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
PIC18FXX8
20.4.1 A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16 bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 20-3 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ‘0’s. When an
A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
FIGURE 20-3:
A/D RESULT JUSTIFICATION
10-bit Result
ADFM = 1
ADFM = 0
7
2107
0
0000 00
ADRESH
ADRESL
10-bit Result
Right Justified
7
0765
0
0000 00
ADRESH
ADRESL
10-bit Result
Left Justified
 2004 Microchip Technology Inc.
DS41159D-page 247