PIC18FXX8 Datasheet, PDF (311/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
NEGF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Negate f
[ label ] NEGF f [,a]
0 ≤ f ≤ 255
a ∈ [0,1]
(f)+1→f
N, OV, C, DC, Z
0110 110a ffff ffff
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
NEGF REG, 1
Before Instruction
REG =
After Instruction
REG =
0011 1010 [0x3A]
1100 0110 [0xC6]
NOP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
No Operation
[ label ] NOP
None
No operation
None
0000 0000
1111 xxxx
No operation.
1
1
0000
xxxx
0000
xxxx
Q2
No
operation
Q3
No
operation
Q4
No
operation
Example:
None.
 2004 Microchip Technology Inc.
DS41159D-page 309