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PIC18FXX8 Datasheet, PDF (305/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module | |||
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PIC18FXX8
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] INCFSZ f [,d [,a]]
Operands:
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
Operation:
(f) + 1 â dest,
skip if result = 0
Status Affected: None
Encoding:
0011 11da ffff ffff
Description:
The contents of register âfâ are
incremented. If âdâ is â0â, the result is
placed in W. If âdâ is â1â, the result is
placed back in register âfâ (default).
If the result is â0â, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction. If âaâ is â0â, the
Access Bank will be selected,
overriding the BSR value. If âaâ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register âfâ
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
Write to
destination
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE INCFSZ CNT
NZERO :
ZERO :
Before Instruction
PC
=
After Instruction
CNT =
If CNT =
PC
=
If CNT â
PC
=
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
INFSNZ
Increment f, Skip if not 0
Syntax:
[ label ] INFSNZ f [,d [,a]]
Operands:
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
Operation:
(f) + 1 â dest,
skip if result â 0
Status Affected: None
Encoding:
0100 10da ffff ffff
Description:
The contents of register âfâ are
incremented. If âdâ is â0â, the result is
placed in W. If âdâ is â1â, the result is
placed back in register âfâ (default).
If the result is not â0â, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If âaâ is â0â, the Access Bank
will be selected, overriding the BSR
value. If âaâ = 1, then the bank will be
selected as per the BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register âfâ
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
Write to
destination
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
ZERO
NZERO
INFSNZ REG
Before Instruction
PC
=
After Instruction
REG =
If REG â
PC
=
If REG =
PC
=
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
 2004 Microchip Technology Inc.
DS41159D-page 303
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