PIC18FXX8 Datasheet, PDF (90/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
8.4 IPR Registers
The Interrupt Priority (IPR) registers contain the individ-
ual priority bits for the peripheral interrupts. Due to the
number of peripheral interrupt sources, there are three
Peripheral Interrupt Priority registers (IPR1, IPR2 and
IPR3). The operation of the priority bits requires that
the Interrupt Priority Enable bit (IPEN) be set.
REGISTER 8-10:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP⁽¹⁾
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
R/W-1
SSPIP
R/W-1
CCP1IP
bit 7
R/W-1
TMR2IP
R/W-1
TMR1IP
bit 0
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit⁽¹⁾
1 = High priority
0 = Low priority
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RCIP: USART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TXIP: USART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159D-page 88
 2004 Microchip Technology Inc.