PIC18FXX8 Datasheet, PDF (44/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
TCY0
Fetch 1
2. MOVWF PORTB
3. BRA SUB_1
4. BSF PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
TCY1
Execute 1
Fetch 2
TCY2
Execute 2
Fetch 3
TCY3
TCY4
TCY5
Execute 3
Fetch 4
Flush
Fetch SUB_1
Execute SUB_1
Note: All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is
“flushed” from the pipeline while the new instruction is being fetched and then executed.
EXAMPLE 4-3: INSTRUCTIONS IN PROGRAM MEMORY
Instruction
Opcode
Memory
—
MOVLW 055h
GOTO 000006h
0E55h
0EF03h, 0F000h
55h
0Eh
03h
0EFh
00h
MOVFF 123h, 456h
—
0C123h, 0F456h
0F0h
23h
0C1h
56h
0F4h
Address
000007h
000008h
000009h
00000Ah
00000Bh
00000Ch
00000Dh
00000Eh
00000Fh
000010h
000011h
000012h
DS41159D-page 42
 2004 Microchip Technology Inc.