PIC18FXX8 Datasheet, PDF (203/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
19.2 CAN Module Registers
Note: Not all CAN registers are available in the
Access Bank.
There are many control and data registers associated
with the CAN module. For convenience, their
descriptions have been grouped into the following
sections:
• Control and Status Registers
• Transmit Buffer Registers (Data and Control)
• Receive Buffer Registers (Data and Control)
• Baud Rate Control Registers
• I/O Control Register
• Interrupt Status and Control Registers
19.2.1 CAN CONTROL AND STATUS
REGISTERS
The registers described in this section control the
overall operation of the CAN module and show its
operational status.
REGISTER 19-1:
CANCON: CAN CONTROL REGISTER
R/W-1 R/W-0 R/W-0 R/W-0
REQOP2 REQOP1 REQOP0 ABAT
bit 7
R/W-0
WIN2
R/W-0
WIN1
R/W-0
WIN0
U-0
—
bit 0
bit 7-5
bit 4
bit 3-1
bit 0
REQOP2:REQOP0: Request CAN Operation Mode bits
1xx = Request Configuration mode
011 = Request Listen Only mode
010 = Request Loopback mode
001 = Request Disable mode
000 = Request Normal mode
ABAT: Abort All Pending Transmissions bit
1 = Abort all pending transmissions (in all transmit buffers)
0 = Transmissions proceeding as normal
WIN2:WIN0: Window Address bits
This selects which of the CAN buffers to switch into the Access Bank area. This allows access
to the buffer registers from any data memory bank. After a frame has caused an interrupt, the
ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer. See
Example 19-1 for code example.
111 = Receive Buffer 0
110 = Receive Buffer 0
101 = Receive Buffer 1
100 = Transmit Buffer 0
011 = Transmit Buffer 1
010 = Transmit Buffer 2
001 = Receive Buffer 0
000 = Receive Buffer 0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
 2004 Microchip Technology Inc.
DS41159D-page 201