PIC18FXX8 Datasheet, PDF (104/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
9.4 PORTD, TRISD and LATD
Registers
Note: This port is only available on the
PIC18F448 and PIC18F458.
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register for the port is TRISD.
Setting a TRISD bit (= 1) will make the corresponding
PORTD pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISD
bit (= 0) will make the corresponding PORTD pin an
output (i.e., put the contents of the output latch on the
selected pin).
Read-modify-write operations on the LATD register
read and write the latched output value for PORTD.
PORTD uses Schmitt Trigger input buffers. Each pin is
individually configurable as an input or output.
PORTD can be configured as an 8-bit wide, micro-
processor port (Parallel Slave Port or PSP) by setting
the control bit PSPMODE (TRISE<4>). In this mode,
the input buffers are TTL. See Section 10.0 “Parallel
Slave Port” for additional information.
PORTD is also multiplexed with the analog comparator
module and the ECCP module.
EXAMPLE 9-4:
CLRF PORTD
CLRF LATD
MOVLW
MOVWF
MOVLW
07h
CMCON
0CFh
MOVWF TRISD
INITIALIZING PORTD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; comparator off
; Value used to
; initialize data
; direction
; Set RD3:RD0 as inputs
; RD5:RD4 as outputs
; RD7:RD6 as inputs
FIGURE 9-9:
PORTD BLOCK DIAGRAM IN I/O PORT MODE
PORT/PSP Select
PSP Data Out
VDD
RD LATD
P
Data Bus
WR LATD
or
PORTD
WR TRISD
RD TRISD
PSP Read
DQ
CK Q
Data Latch
DQ
CK Q
TRIS Latch
N
Vss
QD
EN
Schmitt
Trigger
RD0/PSP0/
C1IN+ pin⁽¹⁾
RD PORTD
PSP Write
C1IN+
Note 1: I/O pins have diode protection to VDD and VSS.
DS41159D-page 102
 2004 Microchip Technology Inc.