PIC18FXX8 Datasheet, PDF (129/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
PIR1
PIE1
IPR1
GIE/
GIEH
PSPIF⁽¹⁾
PSPIE⁽¹⁾
PSPIP⁽¹⁾
PEIE/
GIEL
ADIF
ADIE
ADIP
TMR0IE INT0IE
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
RBIE TMR0IF INT0IF
RBIF 0000 000x 0000 000u
SSPIF
SSPIE
SSPIP
CCP1IF
CCP1IE
CCP1IP
TMR2IF
TMR2IE
TMR2IP
TMR1IF
TMR1IE
TMR1IP
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
TRISD
PORTD Data Direction Register
1111 1111 1111 1111
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
T1CON
RD16
— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
CCPR1L Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
CCP1CON
—
—
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF TMR3IF ECCP1IF -0-0 0000 -0-0 0000
PIE2
—
CMIE
—
EEIE
BCLIE LVDIE TMR3IE ECCP1IE -0-0 0000 -0-0 0000
IPR2
—
CMIP
—
EEIP
BCLIP LVDIP TMR3IP ECCP1IP -1-1 1111 -1-1 1111
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
T3CON
RD16 T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
 2004 Microchip Technology Inc.
DS41159D-page 127