PIC18FXX8 Datasheet, PDF (361/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
FIGURE 27-23: A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK 132
A/D DATA
9
8 7 ^{... ...} 2
1
0
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
NEW_DATA
TCY
DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
2: This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input.
TABLE 27-24: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/d Clock Period
PIC18FXX8
PIC18LFXX8
1.6
20⁽⁵⁾
µs TOSC based, VREF ≥ 3.0V
3.0
20⁽⁵⁾
µs TOSC based, VREF full range
PIC18FXX8
2.0
6.0 µs A/D RC mode
PIC18LFXX8
3.0
9.0 µs A/D RC mode
131 TCNV Conversion Time
11
12
TAD
(not including acquisition time) (Note 1)
132 TACQ Acquisition Time (Note 3)
15
—
µs -40°C ≤ Temp ≤ +125°C
10
—
µs 0°C ≤ Temp ≤ +125°C
135 TSWC Switching Time from Convert → Sample
— (Note 4)
136 TAMP Amplifier Settling Time (Note 2)
1
—
µs This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
Note 1:
2:
3:
4:
5:
ADRES register may be read on the following TCY cycle.
See Section 20.0 “Compatible 10-Bit Analog-to-Digital Converter (A/D) Module” for minimum
conditions when input voltage has changed more than 1 LSb.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AVDD to AVSS or AVSS to AVDD). The source impedance (RS) on the input channels
is 50Ω.
On the next Q4 cycle of the device clock.
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
 2004 Microchip Technology Inc.
DS41159D-page 359