PIC18FXX8 Datasheet, PDF (240/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
FIGURE 19-10: ERROR MODES STATE DIAGRAM
Reset
RXERRCNT < 127 or
TXERRCNT < 127
Error-
Active
Error-
Passive
RXERRCNT > 127 or
TXERRCNT > 127
TXERRCNT > 255
Bus-
Off
128 occurrences of
11 consecutive
“recessive” bits
19.13 CAN Interrupts
The module has several sources of interrupts. Each of
these interrupts can be individually enabled or
disabled. The CANINTF register contains interrupt
flags. The CANINTE register contains the enables for
the 8 main interrupts. A special set of read-only bits in
the CANSTAT register, the ICODE bits, can be used in
combination with a jump table for efficient handling of
interrupts.
All interrupts have one source, with the exception of the
error interrupt. Any of the error interrupt sources can set
the error interrupt flag. The source of the error interrupt
can be determined by reading the Communication
Status register, COMSTAT.
The interrupts can be broken up into two categories:
receive and transmit interrupts.
The receive related interrupts are:
• Receive Interrupts
• Wake-up Interrupt
• Receiver Overrun Interrupt
• Receiver Warning Interrupt
• Receiver Error-Passive Interrupt
The transmit related interrupts are:
• Transmit Interrupts
• Transmitter Warning Interrupt
• Transmitter Error-Passive Interrupt
• Bus-Off Interrupt
19.13.1 INTERRUPT CODE BITS
The source of a pending interrupt is indicated in the
ICODE (Interrupt Code) bits of the CANSTAT register
(ICODE<2:0>). Interrupts are internally prioritized such
that the higher priority interrupts are assigned lower
ICODE values. Once the highest priority interrupt con-
dition has been cleared, the code for the next highest
priority interrupt that is pending (if any) will be reflected
by the ICODE bits (see Table 19-3, following page).
Note that only those interrupt sources that have their
associated CANINTE enable bit set will be reflected in
the ICODE bits.
19.13.2 TRANSMIT INTERRUPT
When the transmit interrupt is enabled, an interrupt will
be generated when the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. The TXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU resetting the TXBnIF bit to a ‘0’.
19.13.3 RECEIVE INTERRUPT
When the receive interrupt is enabled, an interrupt will
be generated when a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving
the EOF field. The RXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU resetting the RXBnIF bit to a ‘0’.
DS41159D-page 238
 2004 Microchip Technology Inc.