PIC18FXX8 Datasheet, PDF (208/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
19.2.2 CAN TRANSMIT BUFFER
REGISTERS
This section describes the CAN Transmit Buffer
registers and their associated control registers.
REGISTER 19-4:
TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS
U-0
R-0
R-0
R-0
R/W-0
U-0
—
TXABT TXLARB TXERR TXREQ
—
bit 7
R/W-0
TXPRI1
R/W-0
TXPRI0
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Unimplemented: Read as ‘0’
TXABT: Transmission Aborted Status bit
1 = Message was aborted
0 = Message was not aborted
TXLARB: Transmission Lost Arbitration Status bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit
1 = Requests sending a message. Clears the TXABT, TXLARB and TXERR bits.
0 = Automatically cleared when the message is successfully sent
Note: Clearing this bit in software while the bit is set will request a message abort.
Unimplemented: Read as ‘0’
TXPRI1:TXPRI0: Transmit Priority bits
11 = Priority Level 3 (highest priority)
10 = Priority Level 2
01 = Priority Level 1
00 = Priority Level 0 (lowest priority)
Note: These bits set the order in which the Transmit Buffer will be transferred. They do
not alter the CAN message identifier.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159D-page 206
 2004 Microchip Technology Inc.