PIC18FXX8 Datasheet, PDF (27/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
3.0 RESET
The PIC18FXX8 differentiates between various kinds
of RESET:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
d) Watchdog Timer (WDT) Reset during normal
operation
e) Programmable Brown-out Reset (PBOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset”
state on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during Sleep and by the
RESET instruction.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR are set or cleared differently in different
Reset situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
Reset. See Table 3-3 for a full description of the Reset
states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
A WDT Reset does not drive MCLR pin low.
FIGURE 3-1:
RESET
Instruction
Stack
Pointer
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
External Reset
MCLR
WDT
Module
Sleep
WDT
Time-out
Reset
VDD Rise
Detect
VDD
Power-on Reset
Brown-out
Reset
BOREN
S
OST/PWRT
OST
OSC1
10-bit Ripple Counter
R
On-chip
RC OSC⁽¹⁾
PWRT
10-bit Ripple Counter
Chip_Reset
Q
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 3-1 for time-out situations.
Enable PWRT
Enable OST⁽²⁾
 2004 Microchip Technology Inc.
DS41159D-page 25