PIC18FXX8 Datasheet, PDF (204/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
REGISTER 19-2:
CANSTAT: CAN STATUS REGISTER
R-1
R-0
R-0
U-0
OPMODE2 OPMODE1 OPMODE0 —
bit 7
R-0
R-0
R-0
ICODE2 ICODE1 ICODE0
U-0
—
bit 0
bit 7-5
bit 4
bit 3-1
bit 0
OPMODE2:OPMODE0: Operation Mode Status bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Configuration mode
011 = Listen Only mode
010 = Loopback mode
001 = Disable mode
000 = Normal mode
Note: Before the device goes into Sleep mode, select Disable mode.
Unimplemented: Read as ‘0’
ICODE2:ICODE0: Interrupt Code bits
When an interrupt occurs, a prioritized coded interrupt value will be present in the
ICODE2:ICODE0 bits. These codes indicate the source of the interrupt. The ICODE2:ICODE0
bits can be copied to the WIN2:WIN0 bits to select the correct buffer to map into the Access
Bank area. See Example 19-1 for code example.
111 = Wake-up on interrupt
110 = RXB0 interrupt
101 = RXB1 interrupt
100 = TXB0 interrupt
011 = TXB1 interrupt
010 = TXB2 interrupt
001 = Error interrupt
000 = No interrupt
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159D-page 202
 2004 Microchip Technology Inc.