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| PIC18FXX8 Datasheet, PDF (194/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module | |||
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PIC18FXX8
FIGURE 18-5:
ASYNCHRONOUS RECEPTION
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
Start
bit bit 0 bit 1
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCREG
Start
bit 7/8 Stop bit
bit
Word 2
RCREG
bit 7/8 Stop
bit
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 18-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend:
Note 1:
GIE/GIEH
PSPIF(1)
PSPIE(1)
PSPIP(1)
PEIE/GIEL TMR0IE
ADIF
RCIF
ADIE
RCIE
ADIP
RCIP
INT0IE
TXIF
TXIE
TXIP
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF INT0IF RBIF
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
0000 000x
0000 0000
0000 0000
1111 1111
0000 000u
0000 0000
0000 0000
1111 1111
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000u
USART Receive Register
0000 0000 0000 0000
CSRC
TX9
TXEN SYNC
â
BRGH TRMT TX9D 0000 -010 0000 -010
Baud Rate Generator Register
0000 0000 0000 0000
x = unknown, - = unimplemented locations read as â0â. Shaded cells are not used for asynchronous reception.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as â0âs.
DS41159D-page 192
 2004 Microchip Technology Inc.
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