PIC18FXX8 Datasheet, PDF (316/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
RLNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Left f (no carry)
[ label ] RLNCF f [,d [,a]]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n + 1>,
(f<7>) → dest<0>
N, Z
0100 01da ffff ffff
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
register f
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
RLNCF REG
Before Instruction
REG =
After Instruction
REG =
1010 1011
0101 0111
RRCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Right f through Carry
[ label ] RRCF f [,d [,a]]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
C, N, Z
0011 00da ffff ffff
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
C
register f
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
RRCF REG, W
Before Instruction
REG =
C
=
After Instruction
REG =
W
=
C
=
1110 0110
0
1110 0110
0111 0011
0
DS41159D-page 314
 2004 Microchip Technology Inc.