PIC18FXX8 Datasheet, PDF(75/402 Page) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

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PIC18FXX8 Datasheet, PDF (75/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

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PIC18FXX8

EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

WRITE_WORD_TO_HREGS

MOVFW POSTINC0, W

MOVWF TABLAT

TBLWT+*

DECFSZ

BRA

PROGRAM_MEMORY

BSF

BCF

BSF

COUNTER

WRITE_WORD_TO_HREGS

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

; get low byte of buffer data

; present data to table latch

; write data, perform a short write

; to internal TBLWT holding register.

; loop until buffers are full

; point to FLASH program memory

; access FLASH program memory

; enable write to memory

Required

Sequence

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

NOP

BSF

DECFSZ

BRA

BCF

INTCON, GIE

55h

EECON2

0AAh

EECON2

EECON1, WR

INTCON, GIE

COUNTER_HI

PROGRAM_LOOP

EECON1, WREN

; disable interrupts

; write 55h

; write 0AAh

; start program (CPU stall)

; re-enable interrupts

; loop until done

; disable write to memory

6.5.2 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

6.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and repro-

grammed if needed.The WRERR bit is set when a write

operation is interrupted by a MCLR Reset or a WDT

Time-out Reset during normal operation. In these

situations, users can check the WRERR bit and rewrite

the location.

6.5.4

PROTECTION AGAINST SPURIOUS

WRITES

To reduce the probability against spurious writes to

Flash program memory, the write initiate sequence

must also be followed. See Section 24.0 âSpecial

Features of the CPUâ for more detail.

6.6 Flash Program Operation During

Code Protection

See Section 24.0 âSpecial Features of the CPUâ for

details on code protection of Flash program memory.

ï£© 2004 Microchip Technology Inc.

DS41159D-page 73

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