PIC18FXX8 Datasheet, PDF (292/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
BCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Bit Clear f
[ label ] BCF
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
0 → f<b>
None
f,b[,a]
1001 bbba ffff ffff
Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’,
the Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then the
bank will be selected as per the BSR
value (default).
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
BCF
FLAG_REG, 7
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
BN
Branch if Negative
Syntax:
[ label ] BN n
Operands:
-128 ≤ n ≤ 127
Operation:
if Negative bit is ‘1’
(PC) + 2 + 2n → PC
Status Affected: None
Encoding:
1110 0110 nnnn nnnn
Description:
If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruc-
tion, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
Q2
Read literal
‘n’
No
operation
Q2
Read literal
‘n’
Q3
Process
Data
No
operation
Q3
Process
Data
Q4
Write to PC
No
operation
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Negative =
PC
=
If Negative =
PC
=
BN Jump
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
DS41159D-page 290
 2004 Microchip Technology Inc.