PIC18FXX8 Datasheet, PDF (301/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
CPFSGT
Compare f with W, Skip if f > W
Syntax:
[ label ] CPFSGT f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) − (W),
skip if (f) > (W)
(unsigned comparison)
Status Affected: None
Encoding:
0110 010a ffff ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ‘f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
CPFSGT REG
NGREATER :
GREATER :
Before Instruction
PC
=
W
=
After Instruction
If REG
>
PC
=
If REG
≤
PC
=
Address (HERE)
?
W;
Address (GREATER)
W;
Address (NGREATER)
CPFSLT
Compare f with W, Skip if f < W
Syntax:
[ label ] CPFSLT f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected: None
Encoding:
0110 000a ffff ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ‘f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
NLESS
LESS
CPFSLT REG
:
:
Before Instruction
PC
=
W
=
After Instruction
If REG
<
PC
=
If REG
≥
PC
=
Address (HERE)
?
W;
Address (LESS)
W;
Address (NLESS)
 2004 Microchip Technology Inc.
DS41159D-page 299