PIC18FXX8 Datasheet, PDF (165/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
17.4.4.5 Clock Synchronization and
the CKP bit
If a user clears the CKP bit, the SCL output is forced to
‘0’. Setting the CKP bit will not assert the SCL output
low until the SCL output is already sampled low. If the
user attempts to drive SCL low, the CKP bit will not
assert the SCL line until an external I²C master device
has already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other devices
on the I²C bus have deasserted SCL. This ensures that
a write to the CKP bit will not violate the minimum high
time requirement for SCL (see Figure 17-12).
FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
CKP
WR
SSPCON1
DX
Master device
asserts clock
Master device
deasserts clock
DX – 1
 2004 Microchip Technology Inc.
DS41159D-page 163