PIC18FXX8 Datasheet, PDF (80/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
FIGURE 8-1:
INTERRUPT LOGIC
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR1IF
TMR1IE
TMR1IP
XXXXIF
XXXXIE
XXXXIP
High Priority Interrupt Generation
Low Priority Interrupt Generation
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
IPEN
Additional Peripheral Interrupts
IPEN
GIEL/PEIE
IPEN
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR1IF
TMR1IE
TMR1IP
XXXXIF
XXXXIE
XXXXIP
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
Additional Peripheral Interrupts ^INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Wake-up if in Sleep mode
Interrupt to CPU
Vector to Location
0008h
GIE/GIEH
Interrupt to CPU
Vector to Location
0018h
PEIE/GIEL
GIE/GIEH
DS41159D-page 78
 2004 Microchip Technology Inc.