PIC18FXX8 Datasheet, PDF (353/402 Pages) Microchip Technology – 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

PIC18FXX8
FIGURE 27-15: EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
70
71
72
83
78
79
SDO
80
MSb
79
Bit 6 - - - - - -1
75, 76
SDI
MSb In
Bit 6 - - - -1
74
73
Note: Refer to Figure 27-5 for load conditions.
78
LSb
77
LSb In
TABLE 27-15: EXAMPLE SPI™ MODE REQUIREMENTS, SLAVE MODE TIMING (CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70 TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
TCY
—
71 TscH
SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 —
71A
Single Byte
40
—
72 TscL
SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 —
72A
Single Byte
40
—
73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
100
—
73A TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40 —
74 TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
—
75 TdoR
SDO Data Output Rise Time
PIC18FXX8
—
25
PIC18LFXX8
45
76 TdoF
SDO Data Output Fall Time
—
25
77 TssH2doZ SS ↑ to SDO Output High-Impedance
10
50
78 TscR
SCK Output Rise Time (Master mode) PIC18FXX8
—
25
PIC18LFXX8
45
79 TscF
SCK Output Fall Time (Master mode)
—
25
80 TscH2doV, SDO Data Output Valid after SCK PIC18FXX8
TscL2doV Edge
PIC18LFXX8
—
50
100
83 TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of parameter #73A.
2: Only if parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
 2004 Microchip Technology Inc.
DS41159D-page 351