TDA5230 Datasheet, PDF (99/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
The Bit Change Detector checks the incoming Manchester coded bit data stream for
changes from 'Zero' to 'One' or 'One' to 'Zero'. This is the case if two consecutive chips
are ’One’ or ’Zero’.
The Pattern Detector is searching for a pattern with 16 chips length within the Wake Up
Window. The pattern is configurable via the register WUPAT0 and WUPAT1. The
selection of 1 out of 4 wake up criteria is done via the WUC register:
The four wake up criteria are in detail:
Pattern Detection
The incoming signal must match a dedicated pattern of up to 8 bits or 16 chips. When
the WUW chip counter elapses, the search is stopped. The higher the setting of
WUBCNT the longer it is possible to search for the wake up pattern. The minimum for
the WUBCNT is 0x11!
The pattern detection is stopped either when WUW elapses, or symbol synchronization
is lost.
Equal Bits Detection
Wake up condition is fulfilled if all received bits inside of WUW are either 0 or 1.
WUBCNT holds the number of required equal bits. The higher the setting of WUBCNT
the lower the number of wrong wake ups.
Equal bits detection is stopped if a wrong bit has been detected, or symbol
synchronization is lost.
Random Bits Detection
Wake up condition is fulfilled if there is no code violation inside of WUW. WUBCNT holds
the number of required manchester coded bits. The higher the setting of WUBCNT, the
lower the number of wrong wake ups.
Random bits detection is stopped if a code violation has been detected, or symbol
synchronization is lost.
Valid Data Rate Detection
Wake up condition is fulfilled if symbol synchronization is possible inside of Sync Search
Time out, which is by default 7.625 data bits long. WUBCNT is not used.
This is the weakest wake up criterion, and should be avoided.
Data Sheet
95
Version 4.0, 2007-06-01