TDA5230 Datasheet, PDF (51/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
CMC0: Chip Mode Control Register 0
ADDR: 0x02
Reset Value: 0x40
Bit R/W Description
7 W INITFIFO: Init FIFO at Cycle Start
Initialization of the FIFO can be configured in both Slave Mode and Self
Polling Mode. In Slave Mode, this occurs at the beginning of the Slave Run
Mode. In Self Polling Mode, initialization is done after a Wake up is found
(switching from Self Polling Mode to Run Mode Self Polling).
0: No Init
1: Init FIFO
5 W TOTIMEN: ToTim Timer enable
Time Out Timer is used to return from Run Mode Self Polling to Self Polling
Mode whenever there is no Sync for a specific time.
0: Disable
1: Enable ToTim Timer
4 W FIFOLK: Lock Data FIFO at EOM
0: FIFO lock is disabled
1: FIFO lock is enabled at EOM (see also Chapter 2.4.15 Data FIFO)
CMC1: Chip Mode Control Register 1
ADDR: 0x03
Bit R/W Description
3 W FSINITFIFO: Init FIFO at Frame Start
0: No Init
1: Init
Reset Value: 0x00
Data Sheet
47
Version 4.0, 2007-06-01