TDA5230 Datasheet, PDF (38/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
CMC0: Chip Mode Control Register 0
ADDR: 0x02
Reset Value: 0x40
Bit R/W Description
1 W SLRXEN: Slave Receiver enable
This Bit is used only in Operating Modes Run Mode Slave, Sleep Mode
0: Receiver is in Sleep Mode
1: Receiver is in Run Mode Slave
0 W MSEL: Operating Mode
0: Run Mode Slave, Sleep Mode
1: Self Polling Mode
Reset
Init
Bit:SLRXEN == 1
Bit:MSEL == 0
Initialize RX-Part
Bit:SLRXEN == 1
Bit:MSEL == 0
Bit:SLRXEN == 0
Bit:SLRXEN == 0
Bit:MSEL == 0
Sleep Mode
Chip is idle
Bit:MSEL == 0
Bit:SLRXEN == 0
Bit:MSEL == 0
Run Mode
Slave
Chip is permanently
active
Bit:SLRXEN == 1
Bit:MSEL == 0
Figure 17
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 0
Init
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 0
Initialize RX-Part
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 0
ToTim Timeout == X
Self Polling
Mode
Chip is periodically active
and searching for
WU criteria
Bit:SLRXEN == X
Bit:MSEL == 1
ToTim Timeout == 1
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 0
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 1
Run Mode
Self Polling
Chip is permanently
active
Bit:SLRXEN == X
Bit:MSEL == 1
ToTim Timeout == 0
Global State Diagram
Data Sheet
34
Version 4.0, 2007-06-01