TDA5230 Datasheet, PDF (122/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
CMC0: Chip Mode Control Register 0
ADDR: 0x02
Reset Value: 0x40
Bit R/W Description
7 W INITFIFO: Init FIFO at Cycle Start
This Initialization of the FIFO can be configured in both Slave Mode and Self
Polling Mode. In Slave Mode, this occurs at the beginning of the Slave Run
Mode. In Self Polling Mode, the initialization is done after Wake up found
(switching from Self Polling Mode to Run Mode Self Polling).
0: No Init
1: Init FIFO
4 W FIFOLK: Lock Data FIFO at EOM
0: FIFO lock is disabled
1: FIFO lock is enabled at EOM (see also Chapter FIFO)
CMC1: Chip Mode Control Register 1
ADDR: 0x03
Bit R/W Description
3 W FSINITFIFO: Init FIFO at Frame Start
0: No Init
1: Init
Reset Value: 0x00
2.4.16 Transparent Mode
In addition to the FIFO functionality, the TDA5230 offers the received data in a
Transparent Mode. In this mode, the Manchester decoded data is available at an
external pin.
This is the same data that is written into the FIFO. This means that data is only available
after a frame synchronization. Wake up pattern, RUNIN and TSI are not visible. If the
FIFO is locked, no data will be written in the Tranparent Mode.
Two pins can be configured to act as the RX data output (CLKOUT/RXD or alternatively
RX-RUN/RXD). The pin NINT/NSTR acts as a data strobe signal. The strobe signal is
active high and has a delay of TBIT/16 relative to the data bit and a duration of TBIT/16.
Configuration of the Transparent Mode is done in the CMC1 register.
Data Sheet
118
Version 4.0, 2007-06-01