TDA5230 Datasheet, PDF (75/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
2.4.8.3 RSSI Peak Detector
As mentioned earlier, RSSI is also sampled by an ADC, delivering an 8-bit resolution. All
four RSSI signals are connected to the differential inputs, and True RSSI with optimal
temperature compensation is automatically generated.
The Chip possesses two digital RSSI peak level detectors. The RSSI level from the ADC
is averaged over four samples before it is sent to the two Peak Detectors. This reduces
the influence of single noise peaks.
f_sys
ADC Sampling-
Clock Generation
ADCSPLRDIV
from
RSSI-
Generator
f_ADC
A
D
Divide
by 4
f_ADC/4
Integrate
Dump
RSSI
I&D-Averaging Filter
to
Data-Filter
Compare
Peak-Detector 1
Update
Peak-
Value
Load
Update
Peak-Value
Register
Peak-
Detector
Track-
Control
EOM
RSSI1
FSYNC
PKBITPOS
Compare
Peak-Detector 2
Update
Peak-
Value
Load
RSSI2
RX-RUN
from
FSM
& _{Read-Access to Register RSSI2 from}
SPI-Controller
Figure 34 Peak Detector Unit
Peak Detector 1 is used to measure the input signal power of a received and accepted
data telegram. It is read via SFR RSSI1.
Observation of the RSSI signal starts at the detection of a TSI (FSYNC) and ends with
the detection of EOM. The internal RSSI1 value is cleared after FSYNC. The evaluated
RSSI peak level RSSI1 is transferred to the RSSI1 register at EOM. Starting the
observation of the RSSI level can be delayed by a selectable number of data bits and is
controlled by the register PKBITPOS. A latency in the generation of FSYNC and EOM of
approx. 2..3 bits in relation to the contents of the Peak Detector must be considered.
Within the boundaries described, the register RSSI1 always contains the peak value of
the last completely received data telegram. The register RSSI1 is reset to 0 at power up
reset only.
Data Sheet
71
Version 4.0, 2007-06-01