TDA5230 Datasheet, PDF (139/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
3.1
Detailed register descriptions
Register Descriptions
SPIAT: SPI Address Tracer
ADDR: 0x00
Bit R/W Description
7:0 R Address Tracer Register
Reset Value: 0x00
SPIDT: SPI Data Tracer
ADDR: 0x01
Bit R/W Description
7:0 R Data Tracer Register
Reset Value: 0x00
CMC0: Chip Mode Control Register 0
ADDR: 0x02
Reset Value: 0x40
Bit R/W Description
7 W INITFIFO: Init FIFO at Cycle Start
This Initialization of the FIFO can be configured in both Slave Mode and Self
Polling Mode. In Slave Mode, this happen at the beginning of the Slave Run
Mode. In Self Polling Mode, initialization is done after Wake up found
(switching from Self Polling Mode to Run Mode Self Polling).
0: No Init
1: Init FIFO
6 W CLKOUTEN: CLKOUT Enable
0: Disable
1: Enable programmable clock output
5 W TOTIMEN: ToTim Timer Enable
Time Out Timer is used to return from Run Mode Self Polling to Self Polling
Mode whenever there is no Sync for a specific time.
0: Disable
1: Enable ToTim Timer
4 W FIFOLK: Lock Data FIFO at EOM
0: FIFO lock is disabled
1: FIFO lock is enabled at EOM
Data Sheet
135
Version 4.0, 2007-06-01