TDA5230 Datasheet, PDF (119/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
2.4.15 Data FIFO
The Data FIFO is the storage for the received data frames. It is written during data
reception. The host microcontroller is able to start reading via SPI right after frame sync
(interrupt). The FIFO can store up to 128 received data bits. If the expected data
transmission contains more bits (note that in TSI 8-Bit Mode Extended the first bit is used
to indicate which of the two TSI pattern has matched), reading must start after frame
sync to prevent an overrun.
Architecture:
The 128-bit data FIFO is based on a bit addressable 2-port memory architecture.
Data
from
Digital-
Receiver
Data Clock
from FSM
INITFIFO
FSINITFIFO
InitFIFO
Write Address
Pointer
(Up-Counter)
ENABLE
RESET
Write-Port
Bit-Address
In
1 of 8 Decoder
byte 0
byte 1
byte 2
byte 3
byte 4
byte 5
byte 6
12b8y-teb7 it
Memobryyte-8Array
byte 9
byte 10
byte 11
byte 12
byte 13
byte 14
byte 15
8 to 1 MUX
Out
Bit-Address
Read-Port
Read Address
Pointer
(Up-Counter)
RESET
ENABLE
SCLK
to
SPI-Bus
from
Digital-
Receiver
FSync
EOM
FIFOLK
FIFO-
Controller
FIFO-Overflow
# of Valid Bits
SDO-Frame
Generator
SDO
fifolk
to FSM
Figure 60 Data FIFO
The write port is controlled by the Digital Receiver using the Write Address Pointer.
Writing data into the FIFO starts with the detection of a TSI. The Write Address Pointer
is incremented with each data clock signal generated by the Digital Receiver. The read
port is controlled by the SPI controller using the Read Address Pointer. Each bit read
from the SPI controller increments the Read Address Pointer. The Read and Write
Data Sheet
115
Version 4.0, 2007-06-01