TDA5230 Datasheet, PDF (163/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Dual: ATSILENB and BTSILENB: TSI B Length
ADDR: 0x84 and 0xA4
Bit R/W Description
4:0 W TSI B Length (in chips):
(0x11 up to 0x1F not used)
Min: 00h =0 bit (see also ATSILENA)
Max: 10h = 16 chips = 8 bits
Register Descriptions
Reset Value: 0x00
Dual: ATSIGAP and BTSIGAP: TSI GAP
ADDR: 0x85 and 0xA5
Reset Value: 0x00
Bit R/W Description
7:3 W TSIGAP: TSI Gap (T/2 bit resolution)
1Fh: 15 1/2 bits gap
00h: 0 bit gap
TSIGAP is used to lock the PLL after TSI A is found, if the TSI detection
mode 10b is selected.
2:0 W GAPVAL: TSI Gap (T/16 bit resolution)
111b: 7/16 bit gap
000b: 0 bit gap
GAPVAL is used to correct the DCO phase after TSIGAP time, if the
TSIMODE.TSIGRSYN is disabled
Dual: ATSIPTA0 and BTSIPTA0: TSI Data Reference Low Byte A
ADDR: 0x86 and 0xA6
Reset Value: 0x00
Bit R/W Description
7:0 W TSIPTA0: Data Pattern for TSI comparison : Bit 7...Bit 0(LSB) (in chips)
Dual: ATSIPTA1 and BTSIPTA1: TSI Data Reference High Byte A
ADDR: 0x87 and 0xA7
Reset Value: 0x00
Bit R/W Description
7:0 W TSIPTA1: Data Pattern for TSI Comparison: Bit 15(MSB)...Bit 8 (in chips)
Data Sheet
159
Version 4.0, 2007-06-01