TDA5230 Datasheet, PDF (21/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
flexible and configurable frame synchronisation and Message ID scanning feature,
supported by special function registers. Received data of an accepted message is stored
in a FIFO and can be read out via the SPI interface.
A master control unit (MCU), implemented as a finite state machine and a Polling Timer
Unit control all actions of the device and can be configured via Special Function
Registers (SFRs). Various self-polling modes can be set up to achieve a maximum of
autonomous receiver operation. The Transparent Mode Unit defines the functionality of
the pins CLKOUT/RXD, NINT/NSTR and RX-RUN/RXD.
A fully integrated multi-channel PLLdrives the LO ports of the Image-Reject-Mixer. Within
a selected operational frequency band multiple channels are accessible by utilizing the
same reference crystal-frequency. The reference clock of the PLL and the digital section
are provided by a pierce type crystal oscillator that offers on chip fine-tuning to trim out
crystal tolerances. A programmable Clock Generation Unit divides the system clock by
a programmable ratio and drives the CLKOUT/RXD pin.
On chip voltage regulators generate the required internal supply voltages and allow the
IC to be operated at supply voltages between 3 V to 3.6 V and 4.5 V to 5.5 V. The digital
supply of the chip is monitored by a brown out detector and is equipped with a built-in
reset generator. Every device contains a unique serial number, which can be read out
via the SPI Interface.
Special Function Register and Control Bit Symbols
CONTROL
Symbolizes unique SFR or SFR-control bit(s).
CONTROL
Symbolizes SFR or SFR-control bit(s) with dual-
configuration capability.
The name (if SFR) starts with A or B, depending on the
selected configuration.
Figure 9 SFR Symbolism
The register names, addresses, and control bits for each function are listed in a table at
the end of this section. Functional descriptions of all registers are provided in Chapter 3
Register Descriptions.
Data Sheet
17
Version 4.0, 2007-06-01