TDA5230 Datasheet, PDF (94/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
T_nom / 16
EOM
from slicer
timing extrapolation
phase
detector
loop
filter
digital
controlled
oscillator
symbol
sync found
recovered
clock
T_nom / 2
T_nom / 2
Figure 44 Clock Recovery (ADPLL)
Clock-Recovery is realized as standard ADPLL¹⁾ PI-regulator with Timing-Extrapolation
Unit for fast setting.
The Clock Recovery locks after 4 correct Manchester coded bits, independent of duty
cycle (35%, 65%) and data rate (+10%, -10%). After locking, the clock must be stable
and has to follow the reference input. Therefore, a rapid setting procedure and a slow
PLL are achieved.
If the PLL is locked the reference signal from the Clock Recovery Slicer is used in the
phase detector block to compute the actual error. The error is used in the PI loop filter to
set the digital controlled oscillator running frequency. For the P, I and Timing
Extrapolation Unit settings the default values for the CDR0 and CDR1 control registers
should be used.
In the unlocked state, the Timing Extrapolation Unit calculates the frequency offset for
the incoming data stream. If 4 correct Manchester coded bits are detected, the RUNIN
length can be set in the CDR2 register, the I-part and the PLL oscillator will be set and
the PLL will be locked.
1) All Digital PLL
Data Sheet
90
Version 4.0, 2007-06-01