TDA5230 Datasheet, PDF (105/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
TSILENA = 8d, TSILENB = 12d
TSIGRSYN = 1
RunIn
Gap RunIn
Incoming Pattern ^{0 0 0 0 0 1 0 S}
000010001111101
Manchester Coded
TSI Pattern Match
FSYNC
Data into FIFO
01010101011001000000010101011001010110101010100110
TSIPTA
76543210
01100100
TSIPTB
1110 9 8 7 6 5 4 3 2 1 0
100101011010
11101
Figure 51 TSI Mode 8-Bit Gap
8-Bit extended Mode: As two correlators working simultaneously in
parallel of up to 16 chips length each, with matching information insertion
This bit is inserted at the beginning of the payload. “0” is inserted, when correlator A has
matched and “1” when correlator B has matched.
TSILENA = 16d, TSILENB = 6d
RunIn
Incoming Pattern ^{0 0 0 0 0 1 0 1 0 1 0 0 1 0}
Manchester Coded
TSI Pattern B Match
FSYNC
Data into FIFO
0101010101100110011001011001
TSIPTB
543210
011001
11010010
Matching Information inserted
Figure 52 TSI Mode 8Bit extended
Selection of a TSI Pattern:
TSI Patterns must be different to the wake up bit stream and the RUNIN to clearly mark
the start of the following data frame. It should be considered that the sychronization has
a tolerance of about one bit. In addition, synchronization is related to data chips, and may
occur in the middle of a data bit. This all must be tolerated by the data framer.
Ideal TSI patterns have at their end a unique bit combination, which may also contain a
number of code violations (CVs).
Data Sheet
101
Version 4.0, 2007-06-01