TDA5230 Datasheet, PDF (172/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Specifications
#
Parameter
G.1 High level input voltage
G.2 Low level input voltage
(except pin P_ON)
G.3 Low level input voltage
at pin P_ON
G.4 High level input leakage
current
G.5 Low level input leakage
current
G.6 High level output voltage
(IOH=-500 µA)
G.7 Low level output voltage
(IOL=500 µA)
Symbol
V_IH
V_IL
Limit Values
Unit
min. typ. max.
0.7•
VDDD
VDD5V V
+0.1
0
0.8
V
Test Conditions *
V_{IL,P_ON}
0
0.5
V
I_LIH
5
µA
I_LIL
-5
µA
V_OH
VDDD-
VDDD V
0.4V
V_OL
0
0.4
V
Timing SPI-Bus
G.1E Clock Frequency
f_C
1.2
MHz
G.2E Clock High Time
t_CH
400
ns
*
G.3E Clock Low Time
t_CL
400
ns
*
G.4E Active Setup Time
t_SSu
400
ns
*
G.5E Not Active Hold Time
t_CS
400
ns
*
G.6E Active Hold Time
t_SHo
400
ns
*
G.7E Not Active Setup Time
t_NSC
400
ns
*
G.8 Deselect Time
t_DS
1
us
*
G.9 SDI Setup Time
t_SDISu
100
ns
*
G.10 SDI Hold Time
t_SDIHo
170
ns
*
G.11 Clock Low To SDO Valid @ t_CDOV
80 pF load
350 ns
*
G.12 Clock Low To SDO Valid @ t_CDOV
10 pF load
270 ns
G.13 SDO Rise Time @ 80 pF load t_SDOri
80
ns
*
G.14 SDO Fall Time @ 80 pF load t_SDOfa
80
ns
*
G.15 SDO Rise Time @ 10 pF load t_SDOri
10
ns
*
G.16 SDO Fall Time @ 10 pF load t_SDOfa
10
ns
*
G.17 SDO Disable Time
t_NSDOZ
270 ns
*
* not subject to production test - verified by characterization/design
Note 1: Timings are generated by finite state machine and are therefore exact values.
Absolute timing tolerances are only influenced by oscillator tolerance.
Data Sheet
168
Version 4.0, 2007-06-01