TDA5230 Datasheet, PDF (109/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
Dual: AEOMDTLEN and BEOMDTLEN: EOM Data Length Limit
ADDR: 0x8B and 0xAB
Reset Value: 0x00
Bit R/W Description
7:0 W DATLEN: Length of Data Field in Telegram
Counting starts after the last TSI Bit
Min: 00h = The next bit after TSI found (when EOM criterion is EMDATLEN)
will generate EOM
Max: FFh
TSI Gap Mode
The TSI GAP Mode is only used if TSI patterns contain a GAP that is not synchronous
to the data rate, e.g. if a GAP is 7.7 data bits, or if a GAP is longer than 10 data bits. In
all other cases, GAPs should be included in the TSI pattern as code violations.
Because of its complexity in configuration, TSI Gap Mode should be used only in
applications as noted above!
For these special protocols, it is possible to lock the actual frequency during a long Code
Violation period inside a TSI (TSIGAP must possess a minimum of 8 chips). After the
lock period, two different re-synchronization modes are available:
• Preferred: phase readjustment only, TSIGRSYN = 0. In this mode, the GAPVAL
value is used to correct the phase after the GAP phase. Overall GAP time can be
defined in T/16 steps. The 5 MSB bits define the real GAP time and the 3 LSB bits
(GAPVAL) the DCO phase correction value.
valid data
RUNIN
TSI A
< 1bit
clock recovery phase
readjustment start point
all space or all mark
valid data
TSI GAP
PLL sync
GAPSync
TSI B
Figure 53 Clock Recovery GAP Re-synchronization mode 0
• Frequency readjustment (in this case, PLL starts from the beginning), TSIGRSYN =
1. In this mode the T/2 GAP resolution can be set in the 5 MSB TSIGAP register bits.
GAPVAL (3 LSB register bits) value is not used.
Data Sheet
105
Version 4.0, 2007-06-01