TDA5230 Datasheet, PDF (140/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Register Descriptions
ADDR: 0x02
Reset Value: 0x40
Bit R/W Description
3 W RMSL: Run Mode Slave Configuration
This Bit is only relevant in Slave Mode, used to define the configuration
0: Configuration A
1: Configuration B
2 W DCE: Dual Configuration Enable
This Bit is only relevant in Self Polling Mode, to define whether both
configurations are used.
0: Only Configuration A is used
1: First Configuration A and then Configuration B is used
1 W SLRXEN: Slave Receiver enable
This Bit is only used in Operating Mode Run Mode Slave/Sleep Mode
0: Receiver is in Sleep Mode
1: Receiver is in Run Mode Slave
0 W MSEL: Operating Mode
0: Run Mode Slave/Sleep Mode
1: Self Polling Mode
CMC1: Chip Mode Control Register 1
ADDR: 0x03
Reset Value: 0x00
Bit R/W Description
6 W HOLD: Holds the chip in the config state (only in Run Mode Slave)
0: Normal Operation
1: Jump into the config state Hold
5 W NINTPOL: Invert NINT Polarity
0: The Interrupt is active low
1: The polarity of the Interrupt is inverted (active high)
4 W XTALTREN: XTAL Trim Enable
0: Trimming is disabled
1: Trimming is enabled
3 W FSINITFIFO: Init FIFO at Frame Start
0: No Init
1: Init
2 W CLKRXDSEL: CLKOUT/RXD Pin Function
0: CLKOUT at Pin CLKOUT/RXD
1: RX-Data out at Pin CLKOUT/RXD
Data Sheet
136
Version 4.0, 2007-06-01