TDA5230 Datasheet, PDF (95/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
The PLL will be unlocked if a code violation of more than the defined length is detected,
which is set in the TVWIN control register. An other criterion for PLL re-synchronization
is an End Of Message (EOM) signalled by the Framer block.
The PLL oscillator generates the Manchester clock (2 * f_data).
The internal PLL lock signal used by the Framer is generated up to 1 bit before RUNIN
ends. The timing extrapolation unit counts the incoming edges and interprets the delay
between two edges as a bit or a chip. Due to the fact that the first edge of a low bit, coded
as ’0’ and ’1,’ rises one Chip later than a “High” Bit, the PLL locks later in this cases. This
can be seen in the figure below. The real needed RUNIN time can be shorter than the
configured RUNIN length in the CDR2 register by up to two chips. This should be
considered when setting the TSI Pattern and/or TSI length. See also Chapter 2.4.13
Frame Synchronization
first edge
RUNIN
1
1
1
1
00001010101010
4 bits detected
Figure 45
first edge
RUNIN
0
0
0
0
00000101010101
4 bits detected
RUNIN generation principle
Number of Required RUNIN Bits:
The number of RUNIN bits specified in SFR RUNLEN must always be 3.5. This setting
defines the duration of the internal synchronisation. Because of internal processing
delays, the pattern length that must be reserved for RUNIN is longer.
The ideal RUNIN pattern is a series of either 1’s or 0’s. This pattern includes the highest
number of edges that can be used for synchronisation. In this case the number of RUNIN
bits is 4.
For any other RUNIN pattern, 5.5 bits should be reserved for RUNIN.
Data Sheet
91
Version 4.0, 2007-06-01